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HCS08 데이터시트(PDF) 77 Page - NXP Semiconductors |
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HCS08 데이터시트(HTML) 77 Page - NXP Semiconductors |
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77 / 316 page ![]() Chapter 6 Parallel Input/Output Control MC9S08SG8 MCU Series Data Sheet, Rev. 8 Freescale Semiconductor 77 6.3 Ganged Output The MC9S08SG8 devices contain a feature that allows for up to eight port pins to be tied together externally to allow higher output current drive. The ganged output drive control register (GNGC) is a write-once register that is used to enabled the ganged output feature and select which port pins will be used as ganged outputs. The GNGEN bit in GNGC enables ganged output. The GNGPS[7:1] bits are used to select which pin will be part of the ganged output. When GNGEN is set, any pin that is enabled as a ganged output will be automatically configured as an output and follow the data, drive strength and slew rate control of PTC0. The ganged output drive pin mapping is shown in Table 6-1. NOTE See the DC characteristics in the electrical section for maximum Port I/O currents allowed for this MCU. When a pin is enabled as ganged output, this feature will have priority over any digital module. An enabled analog function will have priority over the ganged output pin. See Table 2-1 for information on pin priority. Table 6-1. Ganged Output Pin Enable GNGC Register Bits GNGPS7 GNGPS6 GNGPS5 GNGPS4 GNGPS3 GNGPS2 GNGPS1 GNGEN1 1 Ganged output not available on 8-pin packages. PTC3-PTC0 not available on 16-pin packages, however PTC0 control registers are still used to control ganged output. Port Pin 2 2 When GNGEN = 1, PTC0 is forced to an output, regardless of the value in PTCDD0 in PTCDD. PTB5 PTB4 PTB3 PTB2 PTC3 PTC2 PTC1 PTC0 Data Direction Control Pin is automatically configured as output when pin is enabled as ganged output. Data Control PTCD0 in PTCD controls data value of output Drive Strength Control PTCDS0 in PTCDS controls drive strength of output Slew Rate Control PTCSE0 in PTCSE controls slew rate of output |
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