HCS08 datasheet(249/316 Pages) NXP

249 / 316 page

Timer/PWM Module (S08TPMV3)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

249

When BDM is active, the timer counter is frozen (this is the value that will be read by user); the coherency

mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became

active, even if one or both counter halves are read while BDM is active. This assures that if the user was

in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from

the other half of the 16-bit value after returning to normal execution.

In BDM mode, writing any value to TPMxSC, TPMxCNTH or TPMxCNTL registers resets the read

coherency mechanism of the TPMxCNTH:L registers, regardless of the data involved in the write.

16.3.3

TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)

The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM

counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock, and

the overflow flag (TOF) becomes set. Writing to TPMxMODH or TPMxMODL inhibits the TOF bit and

overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000

which results in a free running timer counter (modulo disabled).

Writing to either byte (TPMxMODH or TPMxMODL) latches the value into a buffer and the registers are

updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so:

•

If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written

•

If (CLKSB:CLKSA not = 0:0), then the registers are updated after both bytes were written, and the

TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If

the TPM counter is a free-running counter, the update is made when the TPM counter changes from

0xFFFE to 0xFFFF

The latching mechanism may be manually reset by writing to the TPMxSC address (whether BDM is

active or not).

When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register)

such that the buffer latches remain in the state they were in when the BDM became active, even if one or

both halves of the modulo register are written while BDM is active. Any write to the modulo registers

bypasses the buffer latches and directly writes to the modulo register while BDM is active.

Bit 7

321

Bit 0

Any write to TPMxCNTL clears the 16-bit counter

Reset

Figure 16-9. TPM Counter Register Low (TPMxCNTL)

Bit 15

Bit 8

Reset

Figure 16-10. TPM Counter Modulo Register High (TPMxMODH)

HCS08 데이터시트(PDF) 249 Page - NXP Semiconductors

HCS08 데이터시트(HTML) 249 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL