 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
HCS08 데이터시트(PDF) 266 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
HCS08 데이터시트(HTML) 266 Page - NXP Semiconductors |
|
|
266 / 316 page  MC9S08SG8 MCU Series Data Sheet, Rev. 8 266 Freescale Semiconductor Figure 17-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The host should sample the bit level about 10 cycles after it started the bit time. Figure 17-3. BDC Target-to-Host Serial Bit Timing (Logic 1) HOST SAMPLES BKGD PIN 10 CYCLES BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU SPEEDUP PULSE PERCEIVED START OF BIT TIME HIGH-IMPEDANCE HIGH-IMPEDANCE HIGH-IMPEDANCE BKGD PIN R-C RISE 10 CYCLES EARLIEST START OF NEXT BIT |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
