HCS08 datasheet(299/316 Pages) NXP

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Appendix A Electrical Characteristics

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

299

A.9

Internal Clock Source (ICS) Characteristics

Table A-9. ICS Frequency Specifications (Temperature Range = –40 to 125

C Ambient)

Rating

Symbol

Min

Typ

Max

Unit

Temp Rated1

1 Electrical characteristics only apply to the temperature rated devices marked with x.

Standard

AEC

Grade 0

Internal reference frequency - factory

trimmed

at VDD = 5 V

fint_ft

—

31.25

—

kHz

Internal reference frequency -

untrimmed2

2 TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).

fint_ut

41.66

kHz

Internal reference frequency - user

trimmed

fint_t

31.25

—

39.0625

kHz

D Internal reference startup time

tirefst

—

100

sx

5—

DCO output frequency range -

untrimmed1



value provided for reference: fdco_ut =

1024

 f

int_ut

fdco_ut

25.6

36.86

42.66

MHz

DCO output frequency range -

trimmed

fdco_t

—

MHz

—

MHz

Resolution of trimmed DCO output

frequency at fixed voltage and

temperature (using FTRIM)

f

dco_res_t

—

0.1

0.2

%fdco

Resolution of trimmed DCO output

frequency at fixed voltage and

temperature (not using FTRIM)

f

dco_res_t

—

0.2

0.4

%fdco

Total deviation from actual trimmed

DCO output frequency over voltage

and temperature

f

dco_t

—

+ 0.5

– 1.0

1.5

%fdco

—

+ 0.5

– 1.0

3

%fdco

Total deviation of trimmed DCO output

frequency over fixed voltage and

temperature range of 0

C to 70 C

f

dco_t

—

0.5

1

%fdco

D FLL acquisition time 3

3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or

changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used

as the reference, this specification assumes it is already running.

tacquire

1ms

DCO output clock long term jitter (over

2mS interval) 4

4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

BUS.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.

Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter

percentage for a given interval.

CJitter

—0.02

0.2

%fdco

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