전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

SH7041A 데이터시트(PDF) 384 Page - Renesas Technology Corp

부품명 SH7041A
상세설명  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A 데이터시트(HTML) 384 Page - Renesas Technology Corp

Back Button SH7041A Datasheet HTML 380Page - Renesas Technology Corp SH7041A Datasheet HTML 381Page - Renesas Technology Corp SH7041A Datasheet HTML 382Page - Renesas Technology Corp SH7041A Datasheet HTML 383Page - Renesas Technology Corp SH7041A Datasheet HTML 384Page - Renesas Technology Corp SH7041A Datasheet HTML 385Page - Renesas Technology Corp SH7041A Datasheet HTML 386Page - Renesas Technology Corp SH7041A Datasheet HTML 387Page - Renesas Technology Corp SH7041A Datasheet HTML 388Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 384 / 923 page
background image
346
Phase Count Mode 4: Figure 12.33 shows an example of phase counting mode 4 operation. Table
12.12 lists the up counting and down counting conditions for the TCNT.
Increment
Decrement
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
TCNT value
Time
Figure 12.33 Phase Counting Mode 4 Operation
Table 12.12 Phase Count Mode 4 Up/Down Counting Conditions
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
1 (high level)
Rising edge
Increment
0 (low level)
Falling edge
Rising edge
0 (low level)
Does not count (don’t care)
Falling edge
1 (high level)
1 (high level)
Falling edge
Decrement
0 (low level)
Rising edge
Rising edge
1 (high level)
Does not count (don’t care)
Falling edge
0 (low level)
Phase Counting Mode Application Example: Figure 12.34 shows an example where channel 1
is set to phase counting mode and is teamed with channel 0 to input a two-phase encoder pulse for
a servo motor to accurately detect position and speed.
Channel 1 is set to phase counting mode 1, and the encoder pulse A phase and B phase are input to
the TCLKA and TCLKB pins.
Channel 0 is set so that the TCNT counter is cleared on a TGR0C register compare-match, and the
TGR0A and TGR0C registers are used with the compare-match function to establish the speed
control and position control periods. The TGR0B register is used with the input capture function,
and the TGR0B and TGR0D registers are employed for buffer operation. The channel 1 counter



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com