SH7041A datasheet(499/923 Pages) RENESAS

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13.2.4Register Access

The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in that they

are more difficult to write to. The procedures for writing and reading these registers are given

below.

Writing to the TCNT and TCSR: These registers must be written by a word transfer instruction.

They cannot be written by byte transfer instructions.

The TCNT and TCSR both have the same write address. The write data must be contained in the

lower byte of the written word. The upper byte must be H'5A (for the TCNT) or H'A5 (for the

TCSR) (figure 13.2). This transfers the write data from the lower byte to the TCNT or TCSR.

H'5A

H'FFFF8610

Address:

Writing to the TCNT

Write data

H'A5

H'FFFF8610

Address:

Writing to the TCSR

Write data

Figure 13.2 Writing to the TCNT and TCSR

Writing to the RSTCSR: The RSTCSR must be written by a word access to address

H'FFFF8612. It cannot be written by byte transfer instructions.

Procedures for writing 0 in WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are

different, as shown in figure 13.3.

To write 0 in the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower

byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the

RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The

values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively.

The WOVF bit is not affected.

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