SH7041A datasheet(503/923 Pages) RENESAS

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SH7041A 데이터시트(PDF) 503 Page - Renesas Technology Corp

부품명	SH7041A

상세설명	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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제조업체	RENESAS [Renesas Technology Corp]

홈페이지	http://www.renesas.com

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465

13.3.4Timing of Setting the Overflow Flag (OVF)

In the interval timer mode, when the TCNT overflows, the OVF flag of the TCSR is set to 1 and

an interval timer interrupt is simultaneously requested (figure 13.6).

H'FF

H'00

TCNT

Overflow signal

(internal signal)

OVF

Figure 13.6 Timing of Setting the OVF

13.3.5

Timing of Setting the Watchdog Timer Overflow Flag (WOVF)

When the TCNT overflows in the watchdog timer mode, the WOVF bit of the RSTCSR is set to 1

and a

WDTOVF signal is output. When the RSTE bit is set to 1, TCNT overflow enables an

internal reset signal to be generated for the entire chip (figure 13.7).

H'FF

H'00

TCNT

Overflow signal

(internal signal)

WOVF

Figure 13.7 Timing of Setting the WOVF Bit

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