SH7041A datasheet(511/923 Pages) RENESAS

부품명	SH7041A

상세설명	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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The CPU cannot read or write the TSR directly.

Bit:

R/W:

—

14.2.4

Transmit Data Register (TDR)

The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When

the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in the

TDR into the TSR and starts serial transmission. Continuous serial transmission is possible by

writing the next transmit data in the TDR during serial transmission from the TSR.

The CPU can always read and write the TDR. The TDR is initialized to H'FF by a power-on reset

or in standby mode. Manual reset does not initialize TDR.

Bit:

Initial value:

R/W:

R/W

14.2.5

Serial Mode Register (SMR)

The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication

format and selects the clock source for the baud rate generator.

The CPU can always read and write the SMR. The SMR is initialized to H'00 by a power-on reset

or in standby mode. Manual reset does not initialize SMR.

Bit:

CHR

STOP

CKS1

CKS0

Initial value:

R/W:

R/W

SH7041A 데이터시트(PDF) 511 Page - Renesas Technology Corp