SH7041A datasheet(515/923 Pages) RENESAS

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• Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter.

Bit 5: TE

Description

Transmitter disabled (initial value). The transmit data register empty bit

(TDRE) in the serial status register (SSR) is locked at 1.

Transmitter enabled. Serial transmission starts when the transmit data

0 after writing of transmit data into the TDR. Select the transmit format

in the SMR before setting TE to 1.

• Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver.

Bit 4: RE

Description

Receiver disabled (initial value). Clearing RE to 0 does not affect the

receive flags (RDRF, FER, PER, ORER). These flags retain their

previous values.

Receiver enabled. Serial reception starts when a start bit is detected in

the asynchronous mode, or synchronous clock input is detected in the

clock synchronous mode. Select the receive format in the SMR before

setting RE to 1.

• Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.

The MPIE setting is used only in the asynchronous mode, and only if the multiprocessor mode

bit (MP) in the serial mode register (SMR) is set to 1 during reception. The MPIE setting is

ignored in the clock synchronous mode or when the MP bit is cleared to 0.

Bit 3: MPIE

Description

Multiprocessor interrupts are disabled (normal receive operation) (initial

value). MPIE is cleared when the MPIE bit is cleared to 0, or the

multiprocessor bit (MPB) is set to 1 in receive data.

Multiprocessor interrupts are enabled. Receive-data-full interrupt

requests (RxI), receive-error interrupt requests (ERI), and setting of the

RDRF, FER, and ORER status flags in the serial status register (SSR)

are disabled until data with the multiprocessor bit set to 1 is received.

The SCI does not transfer receive data from the RSR to the RDR, does

not detect receive errors, and does not set the RDRF, FER, and ORER

flags in the serial status register (SSR). When it receives data that

includes MPB = 1, MPB is set to 1, and the SCI automatically clears

MPIE to 0, generates RxI and ERI interrupts (if the TIE and RIE bits in

the SCR are set to 1), and allows the FER and ORER bits to be set.

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