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SH7041A 데이터시트(PDF) 591 Page - Renesas Technology Corp

부품명 SH7041A
상세설명  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A 데이터시트(HTML) 591 Page - Renesas Technology Corp

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To use in combination with simultaneous sampling, set GRP = 1, BUFE1, BUFE0 = B'10, and
CH2 = 0. Buffer operation timing is shown in figure 15.8.
ADDRB
ADDRA
Channel 1
Channel 0
ADST
ADF
ADDRD
ADDRC
Channel 2
Channel 3
Sampling
1
Sampling
3
Sampling
2
Sampling
4
Sampling
5
A/D
conver-
sion 1
A/D
conver-
sion 3
A/D
conver-
sion 2
A/D
conver-
sion 4
Conversion
standby
Conversion standby
Conversion standby
Conversion standby
Conver-
sion
standby
Cleared to 0
by software
Set to 1
by software
Conver-
sion
result 1
Conver-
sion
result 2
Conver-
sion
result 3
Conver-
sion
result 4
Conver-
sion
result 1
Conver-
sion
result 2
Conver-
sion
result 3
Figure 15.8 Buffer Operation Example (Select Scan Mode: Two-Stage One-Group
Operation, When CH2–CH0 = B'001)
Buffer-Only Operation: When performing conversion only on the analog input channels
specified by the BUFE1 and BUFE0 bits, select group mode, and you can select the ADF flag
setting conditions with the CH2–CH0 bits.
Table 15.4 shows conversion during buffer operation and ADF flag setting conditions. The ADF
flag is set at the point in the table when the final conversion has ended. In single mode, conversion
is halted after the ADF flag is set to 1. In scan mode, conversion continues, and the converted data
is stored in sequence in the buffer registers specified by the BUFE1 and BUFE0 bits.



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