EM62100AGH datasheet(18/60 Pages) EMC

18 / 60 page

EM62100

65 COM/132 SEG STN LCD Driver

12 •

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Product Specification (V1.1) 09.13.2005

(This specification is subject to change without further notice)

6.1.3 Serial Interface

When the EM62100 is active (CS1B=”L” and CS2=”H”), the serial data input (SI) and

the serial clock input (SCL) can be received. The serial data can be read from the SI

pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is

converted to 8 bits parallel data in the rising edge of the 8th serial clock for processing.

The RS input is used to determine whether the serial data input is display data

(RS=”H”) or command data (RS=”L”). The RS input is read and used for detection

every 8th rising edge of the serial clock after the chip becomes active. Figure 2 is a

serial interface signal chart.

SCL

CS1B = "L" and CS2 = "H"

Fig. 2

NOTE

1. When the chip is not active, the shift registers and counter are reset to their initial

states.

2. Reading is not possible while in serial interface mode.

3. Caution is required on the SCL signal when it comes to line-end reflections and

external noise. It is recommended that operation be rechecked on the actual

equipment.

6.1.4 Chip Select

The EM62100 has two chip select terminals: CS1B and CS2. The MPU interface or the

serial interface is enabled only when CS1B=”L” and CS2=”H”. When the chip select is

non-active D0 to D7 enter high impedance and the RS, RDB, and WRB inputs are

inactive. When the serial interface is selected, the shift register and the counter are

reset.

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