EM62100AGH datasheet(19/60 Pages) EMC

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EM62100

65 COM/132 SEG STN LCD Driver

Product Specification (V1.1) 09.13.2005

•••• 13

(This specification is subject to change without further notice)

6.2 Access to Display Data RAM and Internal Registers

To match operation frequencies between the MPU and display RAM or internal

internal data bus.

When the MPU writes data to the display RAM, once the data is stored in the bus

holder, then it is written to the display RAM before the next data write cycle. Moreover,

when the MPU reads the display RAM, the first data read cycle (dummy) stores the

read data in the bus holder, and then the data is read from the bus holder to the system

bus at the next data read cycle.

There is a certain restriction in the read sequence of the display RAM. It should be

noted that data of the specified address is not generated by the read instruction issued

immediately after the address setup. This data is generated during the second time

data read. Thus, a dummy read is required whenever the address setup or the write

cycle operation is performed. This relationship is shown in Figure 3.

N+1

N+2

N+1

N+2

Set Address n

Dummy Read

Data read address n Data read address n+1

DATA

MPU

Address

Preset

Internal

Timing

Read

Signal

BUS Holder

Column

Address

Preset

Incremented

Fig. 3

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