MPC821 datasheet(189/242 Pages) NXP

189 / 242 page

Functional Description

MOTOROLA

MPC860TFADS Daughter Board Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

The Fast Ethernet transceiver support two physical interfaces:

RJ45 8pin connector for the twisted pair use this connector is mounted on the board.

Fiber Optic multi mode tranceiver not mounted on the board, it is an optional. The

board design for the HP HFBR-5103 or HFBR-5105.

4•5

Board Control & Status Register - BCSR

Most BCSR control signals and some of BCSR’s status signals are available on the motherboard con-

nectors and on the expansion connectors. The BCSR control most of the functions available on the

MPC860TDB and on the MPC8XXFADS.

See 4•11 "Board Control & Status Register - BCSR" on page 45 of MPC8XXFADS User’s Manual.

TABLE 4-2. BCSR4 The control pins for the LXT970

BIT

MNEMONIC

FUNCTION

PON

DEF

ATT.

UUFEN~

When this signal is active (LOW) it enable the LXT970 device. This signal

connected to the TRSTE signal of the LXT970.

In DTE mode when this pin is high the LXT970 isolate it self from the MII

data interface. In repeater mode when it is high the LXT970 tree state the

MII output pins.

R,W

FETHCFG0

Fast Ethernet CFG0 signal When the LXT970 is in auto negotiation a low to

high transition in this pin cause an auto negotiate to re-start.

When auto negotiation is disabled this input selects operating speed bit

0.13

When this pin is high the 100Mbps is selected 0.13 = 1.

When this pin is low the 10Mbps is selected 0.13 = 0.

R,W

FETHFDE

Full Duplex Enable when auto negotiation is enable the FDE pin of the

LXT970 determine full duplex advertisement capability in combination with

MF4 and CFG1. See the LXT970 documentation.

When auto negotiation is disable the FDE pin of the LXT970 effects full

duplex and determines the value of bit 0.8 Duplex Mode.

When this pin is high Full Duplex in Enable. 0.8 = 1.

When this pin is low Full Duplex is Disable 0.8 = 0.

R,W

FETHCFG1

Fast Ethernet CFG1 signal When the LXT970 is in auto negotiation this pin

determines operating speed advertisement capability in combination with

MF4. see See the LXT970 documentation.

When auto negotiation is disabled this input enables 10Mbps link test

function and directly affects bit 19.8.

When this pin is high, 10Mbps link test is disabled 19.8 = 1.

When this pin is low, 10Mbps link test is enabled 19.8 = 0.

R,W

FETHRST~

Fast Ethernet Reset. When this pin active (LOW) signal is being asserted

the Fast ethernet tranceiver is being reset.

R,W

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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