MPC821 datasheet(39/242 Pages) NXP

39 / 242 page

Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

The performance of the flash memory is shown in TABLE 4-5. "Flash Memory Performance Figures"

below:

The Flash module may disabled / enabled at any time by writing ’1’ / ’0’ the FlashEn~ bit in BCSR1.

4•8

Synchronous Dram

To enhance performance, especially in higher operation frequencies - 4 MBytes of SDRAM is

provided on board. The SDRAM is unbuffered from the MPC bus and is configured as 2 X 512K X

32. Use is done with two MB811171622A-100 chips by Fujitsu or compatibles.

To enhance performance, the SDRAM is unbuffered from the MPC, saving the delay associated with

address and data buffers. Since only 2 memory chips are involved, it does not adversely effect overall

system performance. The SDRAM does not reside on a SIMM but is soldered directly to the FADS

pcb. The SDRAM may be enabled / disabled at any time by writing 1 / 0 to the SDRAMEN bit in

BCSR1. See TABLE 4-10. "BCSR1 Description" on page 48.

The SDRAM’s timing is controlled by UPMB via its assigned CS (See TABLE 4-1. "MPC8XXFADS

Chip Selects’ Assignment" on page 31) line. Unlike a regular dram the synchronous dram has a CS

input in addition to the RAS and CAS signals.

The sdram connection scheme is shown in FIGURE 4-4 "SDRAM Connection Scheme" on page 38.

The SDRAM’s performance figures, are shown in TABLE 4-6. "Estimated SDRAM Performance Fig-

ures":

a. The figures in the table refer to the actual write access. The write operation continues internally

and the device has to be polled for operation completion.

a. One additional cycle for RAS precharge

b. 4-beat Refresh Burst, not including arbitration overhead.

TABLE 4-5. Flash Memory Performance Figures

Number of System Clock Cycles

System Clock Frequency [MHz]

Flash Delay [nsec]

120

Read / Writea Access [Clocks]

TABLE 4-6. Estimated SDRAM Performance Figures

Number of System Clock Cycles

System Clock Frequency [MHz]

Single Read

Single Write

3+1a

2 + 1a

Burst Read

5,1,1,1

3,1,1,1

Burst Write

3,1,1,1 + 1a

2,1,1,1 + 1a

Refresh

21 b

13 b

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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