MPC821 datasheet(62/242 Pages) NXP

62 / 242 page

Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

control status register see TABLE 4-24. "Debug Port Control / Status Register" on page 60.

a. Provided that the PCMCIA channel II pins are configured as debug pins - i.e, VFLS(0:1) signals are available. If

not, the debug port can not be operated correctly.

TABLE 4-24. Debug Port Control / Status Register

BIT

MNEMONIC

Function

I/F

Res

DEF

ATT.

MpcRst

Mpc Reset. When this status only bit indicates when active (high) that

either a SOFT or a HARD reset is driven by the MPC.

-R

TxError

Transmit Error. When this status only bit is active (high) it indicates that

the last transmission towards the MPC, was cut by an internal MPC8XX

reset source. This bit is updated for each byte sent.

-R

InDebug

In Debug Mode. When this status only bit is active (high) it indicates that

the MPC is in debug modea.

-R

4 - 3

DebugClockFreq

Debug Clock Frequency Select. This ﬁeld controls a frequency divider

which divides DSCK. For the division factors and associated DSCK

frequencies see

TABLE 4-25. "DSCK Frequency Select" below.

’00’

R/W

StatusRequest

Status Request. When the host writes this bit active (low), the I/F will issue

a status read request to the host by asserting ADS_REQ line to the host.

When the host writes the control register with this bit negated, no status

read request is issued.

Upon I/F reset this bit wakes-up active.

R/W

DiagLoopBack

Diagnostic Loopback Mode. When this control bit is active (low) the I/F is

placed in Diagnostic Loopback Mode. I.e., DSDI is connected internally to

DSDO, DSDI is tri-stated, and each data byte sent to the I/F data register, is

sampled back into the receive shift register. This mode allows for complete

ADI I/F test, upto transmit and receive shift registers.

Upon I/F reset this bit wakes-up active.

R/W

DebugEntry

Debug Mode Entry. When this bit is active (low), the MPC will enter debug

mode instantly after SOFT reset. When inactive, the MPC will start

executing normally and will enter debug mode only after exception.

Upon I/F reset this bit wakes-up active.

R/W

TABLE 4-25. DSCK Frequency Select

DebugClockFreq

DSCK

Frequency

[MHz]

2.5

1.25

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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