MPC821 datasheet(94/242 Pages) NXP

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MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

"* Rx shift register or the status request bit in the control register is

"* active during a previous host write to the control register.

"* When the host detectes AdsReq asserted, it assertes HstAck in return. HstAck

"* double synchronized from the ADI port and delayed using the bundle delay

"* compensation timer to negate AdsReq. When the host detects AdsReq negated

"* it knows that data is valid to be read. After the host reads the data it

"* negates HstAck.

"* The machine steps through these states :

"* 0 - !ADS_REQ_ACTIVE

"* 1 - ADS_REQ_ACTIVE

"******************************************************************************

equations

AdsReq.clk

= IClk;

AdsReq.ar

= Reset;

AdsReq.oe

= ADS_IS_SELECTED;

S_HstAck.clk = IClk;

DS_HstAck.clk = IClk;

S_HstAck := HstAck;

DS_HstAck := HstAck & S_HstAck;"double synced

state_diagram AdsReq

state !ADS_REQ_ACTIVE:

if ( TxEn.fb & TxWordEnd

#" end of data shift to MPC8XX

ADS_SEND_STATUS) then" end of control write and status required

ADS_REQ_ACTIVE

else

!ADS_REQ_ACTIVE;

state ADS_REQ_ACTIVE:

if ( HOST_READ_ADI & BndTmrExp.fb ) then

!ADS_REQ_ACTIVE

else

ADS_REQ_ACTIVE;

"******************************************************************************

"* ADI control register.

"* The ADI control register is written upon host to ADI write with a

"* D_C~ line is in control mode. It also may be read when StatusRequest~ bit

"* is active.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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