MPC821 datasheet(89/242 Pages) NXP

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MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

"* 2) Host read from adi. In that case AdsReq is NEGATED after that timer

expired, ensuring enough time for data propgation over the bundle.

"* The timer is async reset when both soft and hard reset is applied to the i/f.

"* The timer is sync. reset a clock after it expires.

"* Count starts when either HstReq or HstAck are detected asserted

"* (after proper synchronization)

"* The value upon which the terminal count is assereted, is in the control

"* register. When the interface is reset by the host, this value defaults

"* to its upper bound. Using the diagnostic loop-back mode this value

"* may be re-established for optimal performance. (by means of test & error)

"******************************************************************************

equations

BndDly.ar = Reset;

BndDly.clk = IClk;

when ( ( (HOST_WRITE_ADI_CONTROL # HOST_READ_ADI_CONTROL ) #

(HOST_WRITE_ADI_DATA # HOST_READ_ADI_DATA) & !PdaRst.fb)

& !BndTmrExp.fb) then

BndDly := BndDly.fb +1;

else

BndDly := 0;

BndTmrExp = (BndDly.fb == BUNDLE_DELAY) & !AdsAck ; "delay field

"active low.

"******************************************************************************

"* AdsAck.

"* Host write to ads ack. This state machine generates an automatic ADS_ACK,

"* during a host to ADS write.

"* When the host access the ADS data / control register, an automatic

"* acknowledge is generated, after data has been latched into either the

"* tx shift register or the control register.

"* Acknowledge is released when the host removes its write control line.

(HstReq)

"* The machine steps through these states :

"* 0 - !ADS_ACK_ACTIVE

"* 1 - ADS_ACK_ACTIVE

"******************************************************************************

equations

AdsAck.clk

= IClk;

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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