UPD17062 datasheet(82/298 Pages) RENESAS

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µPD17062

9.11

TIMER CARRY (17H)

9.12

SERIAL INTERFACE WAIT CONTROL (18H)

9.13

IEGNC (1FH)

The IEGNC flag is used for selecting the interrupt detection edge of the INTNC pin and VSYNC pin.

When the flag is set to 0, an interrupt occurs at a rising edge. When the flag is set to 1, an interrupt occurs

at a falling edge.

17H

Exclusive flag for reading timer carry

BTM0CY

This flag is set according to the selected time base,

and reset when the timer carry is read.

18H

Setting of wait timing

SBACK

SIO0NWT

SIO0WRQ1 SIO0WRQ0

2-wire bus mode

Serial I/O mode

Does not wait

Waits when the clock falls with the contents

of the clock counter being 8

Waits when the clock falls with the contents

of the clock counter being 9

Waits when the clock falls with the contents

of the clock counter being 8 after detection

of the start condition

Waits when the contents of the

clock counter become 9

Waits when the contents of the

clock counter become 9

Not to be set

Wait setting

Acknowledgement at 2-wire bus mode

Forced wait

Wait released

IEGVSYN

IEGNC

1FH

Interrupt occurs at the rising edge of the VSYNC pin

Interrupt occurs at the falling edge of the VSYNC pin

Interrupt occurs at the rising edge of the INTNC pin

Interrupt occurs at the falling edge of the INTNC pin

UPD17062 데이터시트(PDF) 82 Page - Renesas Technology Corp

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