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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPD17062 데이터시트(PDF) 98 Page - Renesas Technology Corp |
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UPD17062 데이터시트(HTML) 98 Page - Renesas Technology Corp |
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98 / 298 page  96 µPD17062 Example 2. GET instruction When the 8-bit data of a peripheral register is read, the value of the eight high-order bits (DBF3 and DBF2) of the data register does not change. Of the 8-bit data of the data register, each bit that is not a valid peripheral register bit becomes 0 or unpredictable. Whether the bit becomes 0 or unpredictable is decided in advance for each peripheral register. 10.4.3 State at Peripheral Register Reset The valid bits of each peripheral register are reset as follows: DBF3 DBF2 DBF1 DBF0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Peripheral register b7 b6 b5 b4 b3 b2 b1 b0 GET Data buffer 8 Don't care Don't care 0 or unpredictable 0 or unpredictable The value of the peripheral register is read without alteration. Valid bits Reset Valid bit state Power-on Unpredictable Clock-stop Previous state held CE Previous state held |
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