UPD17062 datasheet(185/298 Pages) RENESAS

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183

µPD17062

(2) At return from clock-stop state

When returning from the back-up state when clock-stop is used to back-up supply voltage at 2.2 V, VDD

must be raised to 3.5 V or greater within 50 ms after the CE pin becomes high level.

As shown in Fig. 14-8, return from the clock-stop state is performed by CE reset. Since the power-on clear

voltage is switched to 3.5 V 50 ms after the CE pin is raised, if VDD is not 3.5 V or greater at this time, power-

on reset is applied.

The same caution is necessary when VDD is dropped.

Fig. 14-8

Return from Clock-Stop State

5 V

0 V

XOUT

VDD

Power-on

clear signal

Timer carry FF

set pulse

3.5 V

2.2 V

CE = low

processing

Normal operation

Back-up

Back-up caused by

clock stop

Power-on

clear voltage

Halt state

50 ms

CE reset

Program start

STOP

0000B

At this point, the power-on

clear voltage is switched to 2.2 V.

Therefore, VDD must not be dropped

below 2.2 V before this point.

At this point, the power-on

clear voltage is switched to 3.5 V.

Therefore, VDD must be raised to

3.5 V or greater before this point.

UPD17062 데이터시트(PDF) 185 Page - Renesas Technology Corp

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