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WM8772SEDS/V 데이터시트(PDF) 44 Page - Wolfson Microelectronics plc |
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WM8772SEDS/V 데이터시트(HTML) 44 Page - Wolfson Microelectronics plc |
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44 / 73 page ![]() WM8772EFT – 32 LEAD TQFP Production Data w PD Rev 4.2 October 2005 44 ADCBCLK/ DACBCLK (Outputs) DOUT ADCLRC/ DACLRC (Outputs) t DL DIN1/2/3 t DDA t DHT t DST Figure 39 Digital Audio Data Timing – Master Mode Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25 oC, Master Mode, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information ADCLRC/DACLRC propagation delay from ADCBCLK/DACBCLK falling edge tDL 0 10 ns DOUT propagation delay from ADCBCLK falling edge tDDA 0 10 ns DIN1/2/3 setup time to DACBCLK rising edge tDST 10 ns DIN1/2/3 hold time from DACBCLK rising edge tDHT 10 ns Table 14 Digital Audio Data Timing – Master Mode |
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