전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

WM8772SEDS/V 데이터시트(PDF) 23 Page - Wolfson Microelectronics plc

부품명 WM8772SEDS/V
상세설명  24-bit, 192kHz 6-Channel Codec with Volume Control
PDF  73 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8772SEDS/V 데이터시트(HTML) 23 Page - Wolfson Microelectronics plc

Back Button WM8772SEDS/V Datasheet HTML 19Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 20Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 21Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 22Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 23Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 24Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 25Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 26Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 27Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 23 / 73 page
background image
Production Data
WM8772EDS – 28 LEAD SSOP
w
PD Rev 4.2 October 2005
23
DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In
both Master and Slave modes DIN1/2/3 are always inputs to the WM8772EDS and DOUT is always
an output. The default is Slave mode.
In Slave mode, LRC and BCLK are inputs to the WM8772EDS (Figure 21). DIN1/2/3 and LRC are
sampled by the WM8772EDS on the rising edge of BCLK. ADC data is output on DOUT and
changes on the falling edge of BCLK.
By setting the control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3 and LRC are
sampled on the falling edge of BCLK and DOUT changes on the rising edge of BCLK.
LRC
DOUT
BCLK
DIN1/2/3
WM8772
CODEC
DSP
ENCODER/
DECODER
3
Figure 21 Slave Mode
In Master mode, LRC and BCLK are outputs from the WM8772EDS (Figure 22). LRC and BCLK are
generated by the WM8772EDS. DIN1/2/3 are sampled by the WM8772EDS on the rising edge of
BCLK so the controller must output DAC data that changes on the falling edge of BCLK. ADC data is
output on DOUT and changes on the falling edge of BCLK.
By setting control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3 are sampled on the
falling edge of BCLK, and DOUT changes on the rising edge of BCLK.
DOUT
BCLK
DIN1/2/3
LRC
WM8772
CODEC
DSP/
ENCODER/
DECODER
3
Figure 22 Master Mode



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com