WM8772SEDSSLASHV datasheet(25/73 Pages) WOLFSON

25 / 73 page

Production Data

WM8772EDS – 28 LEAD SSOP

PD Rev 4.2 October 2005

RIGHT JUSTIFIED MODE

In right justified mode, the LSB of DIN1/2/3 is sampled by the WM8772EDS on the rising edge of

BCLK preceding a LRC transition. The LSB of the ADC data is output on DOUT and changes on the

falling edge of BCLK preceding a LRC transition and may be sampled on the rising edge of BCLK.

LRC are high during the left samples and low during the right samples (Figure 24).

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN1/2/3/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 24 Right Justified Mode Timing Diagram

2S MODE

In I

2S mode, the MSB of DIN1/2/3 is sampled by the WM8772EDS on the second rising edge of

BCLK following a LRC transition. The MSB of the ADC data is output on DOUT and changes on the

first falling edge of BCLK following an LRC transition and may be sampled on the rising edge of

BCLK. LRC are low during the left samples and high during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN1/2/3/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

Figure 25 I

2S Mode Timing Diagram

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