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WM8772SEDS/V 데이터시트(PDF) 19 Page - Wolfson Microelectronics plc |
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WM8772SEDS/V 데이터시트(HTML) 19 Page - Wolfson Microelectronics plc |
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19 / 73 page ![]() Production Data WM8772EDS – 28 LEAD SSOP w PD Rev 4.2 October 2005 19 Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DOUT propagation delay from BCLK falling edge tDD 0 10 ns Table 4 Digital Audio Data Timing – Slave Mode MPU INTERFACE TIMING ML/I2S MC/IWL MD/DM t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS Figure 18 SPI Compatible Control Interface Input Timing Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25 oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated PARAMETER SYMBOL MIN TYP MAX UNIT MC/IWL rising edge to ML/I2S rising edge tSCS 60 ns MC/IWL pulse cycle time tSCY 80 ns MC/IWL pulse width low tSCL 30 ns MC/IWL pulse width high tSCH 30 ns MD/DM to MC/IWL set-up time tDSU 20 ns MC/IWL to MD/DM hold time tDHO 20 ns ML/I2S pulse width low tCSL 20 ns ML/I2S pulse width high tCSH 20 ns ML/I2S rising to MC/IWL rising tCSS 20 ns Table 5 3-Wire SPI Compatible Control Interface Input Timing Information |
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