WM8772SEDSSLASHV datasheet(28/73 Pages) WOLFSON

28 / 73 page

WM8772EDS – 28 LEAD SSOP

Production Data

PD Rev 4.2 October 2005

Figure 32 DSP Mode Audio Interface - Mode B Slave, ADC

ADCLRC

BCK

DOUT

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n-1

LSB

MSB

n-1

RIGHT CHANNEL

NO VALID DATA

Figure 33 DSP Mode Audio Interface - Mode B Master, ADC

In both DSP mode A and mode B, DACL1 is always sent first, followed immediately by DACR1 and

the data words for the other 6 channels. No BCLK edges are allowed between the data words. The

word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right.

POWERDOWN MODES

The WM8772EDS has powerdown control bits allowing specific parts of the WM8772EDS to be

powered off when not being used. Control bit ADCPD powers off the ADC. The three stereo DACs

each have a separate powerdown control bit, DACPD[2:0] allowing individual stereo DACs to be

powered off when not in use. Setting ADCPD and DACPD[2:0] will powerdown everything except the

references VMID and REFADC. These may be powered down by setting PDWN. Setting PDWN will

override all other powerdown control bits. It is recommended that the ADC and DACs are powered

down before setting PDWN.

ZERO DETECT

The WM8772EDS has a zero detect circuit for each DAC channel that detects when 1024

consecutive zero samples have been input. The MUTE pin output may be programmed to output the

zero detect signal (see Table 10) which may then be used to control external muting circuits. A ‘1’ on

MUTE indicates a zero detect. The zero detect may also be used to automatically enable DAC mute

by setting IZD.

DZFM[1:0]

MUTE

All channels zero

Channel 1 zero

Channel 2 zero

Channel 3 zero

Table 10 Zero Flag Output Select

WM8772SEDS/V 데이터시트(PDF) 28 Page - Wolfson Microelectronics plc