전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

WM8772SEDS/V 데이터시트(PDF) 59 Page - Wolfson Microelectronics plc

부품명 WM8772SEDS/V
상세설명  24-bit, 192kHz 6-Channel Codec with Volume Control
PDF  73 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8772SEDS/V 데이터시트(HTML) 59 Page - Wolfson Microelectronics plc

Back Button WM8772SEDS/V Datasheet HTML 55Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 56Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 57Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 58Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 59Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 60Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 61Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 62Page - Wolfson Microelectronics plc WM8772SEDS/V Datasheet HTML 63Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 59 / 73 page
background image
Production Data
WM8772EFT – 32 LEAD TQFP
w
PD Rev 4.2 October 2005
59
CONTROL INTERFACE REGISTERS
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and
right channel DACs from the next audio input sample. No update to the attenuation registers is
required for ATC to take effect.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000010
DAC Channel Control
3
ATC
0
Attenuator Control Mode:
0: Right channels use right
attenuations
1: Right channels use left
attenuations
INFINITE ZERO DETECT ENABLE
Setting the IZD register bit will enable the internal infinite zero detect function:
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000010
DAC Channel Control
4
IZD
0
Infinite zero mute enable
0: Disable infinite zero mute
1: Enable infinite zero mute
With IZD enabled, applying 1024 consecutive zero input samples to each input will cause the
relevant DAC to be muted to VMID. Mute will be removed as soon as that channel receives a non-zero
input.
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are
applied to the left and right DACs:
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
PL[3:0]
Left
Output
Right
Output
0000
Mute
Mute
0001
Left
Mute
0010
Right
Mute
0011
(L+R)/2
Mute
0100
Mute
Left
0101
Left
Left
0110
Right
Left
0111
(L+R)/2
Left
1000
Mute
Right
1001
Left
Right
1010
Right
Right
1011
(L+R)/2
Right
1100
Mute
(L+R)/2
1101
Left
(L+R)/2
1110
Right
(L+R)/2
0000010
DAC Control
8:5
PL[3:0]
1001
1111
(L+R)/2
(L+R)/2



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com