ATAM894 datasheet(13/97 Pages) ATMEL

13 / 97 page

4679D–4BMCU–05/05

ATAM894

A power-on reset pulse is generated by a V

DD rise across the default BOT voltage level (1.7V). A

brown-out reset pulse is generated when V

DD falls below the brown-out voltage threshold. Two

values for the brown-out voltage threshold are programmable via the BOT bit in the SC register.

When the controller runs in the upper supply voltage range with a high system clock frequency,

the high threshold must be used. When it runs with a lower system clock frequency, the low

threshold and a wider supply voltage range may be chosen. For further details, see the electrical

specification and the SC register description for BOT programming.

Figure 5-8.

Brown-out Detection

Note:

BOT = 1, low brown-out voltage threshold 1.7V (is reset value).

BOT = 0, high brown-out voltage threshold 2.0V.

5.3.2

Watchdog Reset

The watchdog's function can be enabled at the WDC register and triggers a reset with every

watchdog counter overflow. To suppress the watchdog reset, the watchdog counter must be

regularly reset by reading the watchdog register address (CWD). The CPU reacts in exactly the

same manner as a reset stimulus from any of the above sources.

5.3.3

External Clock Supervisor

The external input clock supervisor function can be enabled if the external input clock is selected

within the CM- and SC registers of the clock module. The CPU reacts in exactly the same man-

ner as a reset stimulus from any of the above sources.

5.4

Voltage Monitor

The voltage monitor consists of a comparator with an internal voltage reference. It is used to

supervise the supply voltage or an external voltage at the VMI pin. The comparator for the sup-

ply voltage has three internal programmable thresholds: one lower threshold (2.2V), one middle

threshold (2.6 V) and one higher threshold (3.0V). For external voltages at the VMI pin, the com-

parator threshold is set to V

BG = 1.3V. The VMS bit indicates if the supervised voltage is below

(VMS = 0) or above (VMS = 1) this threshold. An interrupt can be generated when the VMS bit is

set or reset to detect a rising or falling slope. A voltage monitor interrupt (INT7) is enabled when

the interrupt mask bit (VIM) is reset in the VMC register.

CPU

Reset

BOT = 1

2.0 V

1.7 V

BOT = 0

d = 1.5 ms (typically)

CPU

Reset

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