ATAM894 datasheet(4/97 Pages) ATMEL

4 / 97 page

4679D–4BMCU–05/05

ATAM894

4.4

Reset Function

During each reset (power-on or brown-out) the configuration register is reset and reloaded with

the data from the configuration memory. This leads to a slightly different behavior compared to

the ROM versions. Both devices switch their I/Os to input during reset but the ROM part has the

mask selected pull-up or pull-down resistors active while the MTP has them removed until the

download is finished.

MARC4 Architecture

5.1

General Description

The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip

peripherals. The CPU is based on the Harvard architecture with physically separate program

memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the

memory bus and the I/O bus, are used for parallel communication between ROM, RAM and

peripherals. This enhances program execution speed by allowing both instruction prefetching,

and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful

integrated interrupt controller with associated eight prioritized interrupt levels supports fast and

efficient processing of hardware events. The MARC4 is designed for the high-level programming

language qFORTH. The core includes both, an expression and a return stack. This architecture

enables high-level language programming without any loss of efficiency or code density.

Figure 5-1.

MARC4 Core

Instruction

decoder

CCR

TOS

ALU

RAM

Program

256 x 4-bit

MARC4 CORE

Clock

Reset

Sleep

Memory bus

I/O bus

Instruction

bus

Reset

System

clock

Interrupt

controller

On-chip peripheral modules

memory

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