ATAM894 datasheet(5/97 Pages) ATMEL

5 / 97 page

4679D–4BMCU–05/05

ATAM894

5.2

Components of MARC4 Core

The core contains ROM, RAM, ALU, program counter, RAM address registers, instruction

decoder and interrupt controller. The following sections describe each functional block in more

detail.

5.2.1

Program Memory

The program memory (EEPROM) is electrically programmable and erasable with the customer

application program. The program memory is addressed by a 12-bit wide program counter and

an additional ROM bank register, thus predefining a maximum linear adressable program bank

size of 4 Kbytes. The upper 2 Kbytes may be exchanged by ROM banking, thus allowing to

address a maximum of 10 Kbytes user program. 8 Kbytes of program memory are available

within the ATAM894. The lowest user (EEP)ROM address segment is taken up by a 512-byte

zero page which contains predefined start addresses for interrupt service routines and special

subroutines accessible with single byte instructions (SCALL).

The corresponding memory map is shown in Figure 5-2. Look-up tables of constants can also be

held in ROM and are accessed via the MARC4’s built-in table instruction.

Figure 5-2.

ROM Map

5.2.1.1

ROM Banking

For customers programming with qFORTH the bank switching is fully supported by the compiler.

The MARC4 switches from one ROM bank to another by writing the new bank number to the

ROM Bank Register (RBR). Conventional program space (power-up bank) resides in ROM bank

0. Each ROM bank consists of a 2 Kbyte address space whereby the lowest 2 Kbyte, the base

bank, is common to all banks, so that addresses between 000h and 7FFh always access the

same ROM data (see Figure 5-2). When ROM banking is used, the compiler will, if necessary,

insert program code to save and restore the condition of the RBR on bank switching.

5.2.2

RAM

The ATAM894 contains 256

× 4-bit wide static random access memory (RAM). It is used for the

expression stack, the return stack and data memory for variables and arrays. The RAM is

addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y.

1F0h

1F8 h

01 0 h

01 8 h

000h

008h

020h

1E 8h

1E 0h

140h

180h

040h

0C 0h

008h

$AUTOSLEEP

$RESET

INT0

INT1

INT2

INT3

INT4

INT5

INT6

INT7

1E 0h

1C 0h

100h

080h

page

000h

Zero page

Base bank

Bank 1

Bank 2

Bank 4

Bank 3

000h

Port D: 00xxb

FFFh

800h

7FFh

Port D: 11xxb

Port D: 10xxb

Port D: 01xxb

000h

1FFh

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