ST72324BJ2 datasheet(64/188 Pages) STMICROELECTRONICS

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On-chip peripherals

ST72324B

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10.1.9

Control register (WDGCR)

10.2

Main clock controller with real-time clock and beeper

(MCC/RTC)

The main clock controller consists of three different functions:

●

a programmable CPU clock prescaler

●

a clock-out signal to supply external devices

●

a real-time clock timer with interrupt capability

Each function can be used independently and simultaneously.

10.2.1

Programmable CPU clock prescaler

The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal

peripherals. It manages Slow power saving mode (see Section 8.2: Slow mode on page 47

for more details).

The prescaler selects the fCPU main clock frequency and is controlled by three bits in the

MCCSR register: CP[1:0] and SMS.

WDGCR

Reset value: 0111 1111 (7Fh)

654

WDGA

T[6:0]

R/W

Table 34.

WDGCR register description

Bit

Name

Function

7WDGA

Activation bit

This bit is set by software and only cleared by hardware after a reset. When

WDGA = 1, the watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

6:0

T[6:0]

7-bit counter (MSB to LSB)

These bits contain the value of the Watchdog counter, which is decremented every

16384 fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh

(T6 is cleared).

Table 35.

Watchdog timer register map and reset values

Address (Hex.) Register label

654

3210

002Ah

WDGCR

reset value

WDGA

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