ST72324BJ2 datasheet(24/188 Pages) STMICROELECTRONICS

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Central processing unit (CPU)

ST72324B

24/188

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is

given by the corresponding bits in the interrupt software priority registers (ISPRx). They can

be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP

instructions.

See Section 7: Interrupts on page 36 for more details.

Zero (Arithmetic Management bit)

This bit is set and cleared by hardware. This bit indicates that the result of the last

arithmetic, logical or data manipulation is zero.

0: The result of the last operation is different from zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Carry/borrow

This bit is set and cleared by hardware and software. It indicates an overflow or an

underflow has occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC

instructions. It is also affected by the ‘bit test and branch’, shift and rotate instructions.

Table 6.

Software interrupt bits

BIt Name

Function

5I1

Software Interrupt Priority 1

The combination of the I1 and I0 bits determines the current interrupt software priority

(see Table 7).

3I0

Software Interrupt Priority 0

The combination of the I1 and I0 bits determines the current interrupt software priority

(see Table 7).

Table 7.

Interrupt software priority selection

Interrupt software priority

Level

Level 0 (main)

Low

High

Level 1

Level 2

Level 3 (= interrupt disable)

Table 5.

Arithmetic management bits (continued)

BIt Name

Function

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