ST72324BJ2 datasheet(43/188 Pages) STMICROELECTRONICS

43 / 188 page

ST72324B

Interrupts

43/188

7.6

External interrupts

7.6.1

I/O port interrupt sensitivity

The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR

sensitivities.

Each external interrupt source can be generated on four (or five) different events on the pin:

●

Falling edge

●

Rising edge

●

Falling and rising edge

●

Falling edge and low level

●

Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity bits in the EICR register can be modified

only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that

interrupts must be disabled before changing sensitivity.

The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits

of the EICR.

Figure 22.

External interrupt control bits

IS10

IS11

EICR

PBOR.3

PBDDR.3

IPB BIT

PB3

ei2 interrupt source

Port B [3:0] interrupts

PB3

PB2

PB1

PB0

IS10

IS11

EICR

PBOR.4

PBDDR.4

PB4

ei3 interrupt source

Port B4 interrupt

IS20

IS21

EICR

PAOR.3

PADDR.3

IPA BIT

PA3

ei0 interrupt source

Port A3 interrupt

IS20

IS21

EICR

PFOR.2

PFDDR.2

PF2

ei1 interrupt source

Port F [2:0] interrupts

PF2

PF1

PF0

Sensitivity

control

Sensitivity

control

Sensitivity

control

ST72324BJ2 데이터시트(PDF) 43 Page - STMicroelectronics

ST72324BJ2 데이터시트(HTML) 43 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL