ST72324BJ2 datasheet(34/188 Pages) STMICROELECTRONICS

34 / 188 page

Supply, reset and clock management

ST72324B

34/188

6.6

SI registers

6.6.1

System integrity (SI) control/status register (SICSR)

SICSR

Reset value: 000x 000x (00h)

654

Res

AVDIE

AVDF

LVDRF

Reserved

WDGRF

R/W

Table 11.

SICSR register description

Bit

Name

Function

Reserved, must be kept cleared

6AVDIE

Voltage Detector Interrupt Enable

This bit is set and cleared by software. It enables an interrupt to be generated

when the AVDF flag changes (toggles). The pending interrupt information is

automatically cleared when software enters the AVD interrupt routine

0: AVD interrupt disabled

1: AVD interrupt enabled

5AVDF

Voltage Detector Flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an

interrupt request is generated when the AVDF bit changes value. Refer to

Figure 17 and to Section 6.5.2: AVD (auxiliary voltage detector) for additional

details.

0: VDD over VIT+(AVD) threshold

1: VDD under VIT-(AVD) threshold

LVDRF

LVD Reset Flag

This bit indicates that the last reset was generated by the LVD block. It is set by

hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag

description for more details. When the LVD is disabled by option byte, the LVDRF

bit value is undefined.

3:1

Reserved, must be kept cleared

WDGRF

Watchdog Reset Flag

This bit indicates that the last reset was generated by the Watchdog peripheral. It is

set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD

reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).

Combined with the LVDRF information, the flag description is given in Table 12.

Table 12.

Reset source flags

Reset sources

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

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