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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST72324BJ2 데이터시트(PDF) 110 Page - STMicroelectronics |
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ST72324BJ2 데이터시트(HTML) 110 Page - STMicroelectronics |
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110 / 188 page  On-chip peripherals ST72324B 110/188 Figure 59. SCI baud rate and extended prescaler block diagram Framing error A framing error is detected when: ● The stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise. ● A break is received. When the framing error is detected: ● the FE bit is set by hardware ● Data is transferred from the Shift register to the SCIDR register. ● No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation. Transmitter Receiver SCIETPR SCIERPR Extended prescaler receiver rate control Extended prescaler transmitter rate control Extended prescaler clock clock Receiver rate Transmitter rate SCIBRR SCP1 fCPU control control SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 /PR /16 Conventional baud rate generator Extended receiver prescaler register Extended transmitter prescaler register |
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