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ST72324BJ2 데이터시트(PDF) 157 Page - STMicroelectronics

부품명 ST72324BJ2
상세설명  8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
PDF  188 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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ST72324BJ2 데이터시트(HTML) 157 Page - STMicroelectronics

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ST72324B
Electrical characteristics
157/188
12.10
Control pin characteristics
12.10.1
Asynchronous RESET pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 107.
Asynchronous RESET pin
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage(1)
0.3xVDD
V
VIH
Input high level voltage(1)
0.7xVDD
Vhys
Schmitt trigger voltage hysteresis(2)
2.5
VOL
Output low level voltage(3)
VDD = 5V, IIO = +2mA
0.2
0.5
V
IIO
Driving current on RESET pin
2
mA
RON
Weak pull-up equivalent resistor
VDD = 5V
20
30
120
k
Ω
tw(RSTL)out Generated reset pulse duration
Internal reset sources
20
30
42(4)
µs
th(RSTL)in
External reset pulse hold time(5)
2.5
µs
tg(RSTL)in Filtered glitch duration
(6)
200
ns
1.
Data based on characterization results, not tested in production.
2.
Hysteresis voltage between Schmitt trigger switching levels.
3.
The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVSS.
4.
Data guaranteed by design, not tested in production.
5.
To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the
RESET pin with a duration below th(RSTL)in can be ignored.
6.
The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy
environments.



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