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ST72324BJ2 데이터시트(PDF) 174 Page - STMicroelectronics |
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ST72324BJ2 데이터시트(HTML) 174 Page - STMicroelectronics |
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174 / 188 page ![]() Device configuration and ordering information ST72324B 174/188 OPT3:1 OSCRANGE[2:0] Oscillator range When the resonator oscillator type is selected, these option bits select the resonator oscillator current source corresponding to the frequency range of the used resonator. When the external clock source is selected, these bits are set to medium power (2 ~ 4 MHz) . 000: Typ. frequency range (LP) = 1 ~ 2 MHz 001: Typ. frequency range (MP) = 2 ~ 4 MHz 010: Typ. frequency range (MS) = 4 ~ 8 MHz 011: Typ. frequency range (HS) = 8 ~ 16 MHz OPT0 PLL OFF PLL activation This option bit activates the PLL which allows multiplication by two of the main input clock frequency. The PLL must not be used with the internal RC oscillator. The PLL is guaranteed only with an input frequency between 2 and 4 MHz. 0: PLL x2 enabled 1: PLL x2 disabled Caution: The PLL can be enabled only if the “OSCRANGE” (OPT3:1) bits are configured to “MP - 2~4 MHz”. Otherwise, the device functionality is not guaranteed. Table 121. Package selection (OPT7) Version Selected package PKG1 J LQFP44/SDIP42 1 K LQFP32/SDIP32 0 Table 120. Option byte 1 bit description (continued) Bit Name Function |
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