ST72324BJ2 datasheet(184/188 Pages) STMICROELECTRONICS

184 / 188 page

Known limitations

ST72324B

184/188

In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.

This may lead to generate one break more than expected.

Occurrence

The occurrence of the problem is random and proportional to the baud rate. With a transmit

frequency of 19200 baud (fCPU = 8MHz and SCIBRR = 0xC9), the wrong break duration

occurrence is around 1%.

Workaround

If this wrong duration is not compliant with the communication protocol in the application,

software can request that an Idle line be generated before the break character. In this case,

the break duration is always correct assuming the application is not doing anything between

the idle and the break. This can be ensured by temporarily disabling interrupts.

The exact sequence is:

Disable interrupts

Reset and set TE (IDLE request)

Set and reset SBK (break request)

Re-enable interrupts

15.2

8/16 Kbyte Flash devices only

15.2.1

39-pulse ICC entry mode

ICC mode entry using ST7 application clock (39 pulses) is not supported. External clock

mode must be used (36 pulses). Refer to the ST7 Flash Programming Reference Manual.

15.2.2

Negative current injection on pin PB0

Negative current injection on pin PB0 degrades the performance of the device and is not

allowed on this pin.

15.3

8/16 Kbyte ROM devices only

15.3.1

Readout protection with LVD

Readout protection is not supported if the LVD is enabled.

15.3.2

I/O Port A and F configuration

When using an external quartz crystal or ceramic resonator, a few fOSC2 clock periods may

be lost when the signal pattern in Table 125 occurs. This is because this pattern causes the

device to enter test mode and return to user mode after a few clock periods. User program

execution and I/O status are not changed, only a few clock cycles are lost.

This happens with either one of the following configurations

●

PA3 = 0, PF4 = 1, PF1 = 0 while PLL option is disabled and PF0 is toggling

●

PA3 = 0, PF4 = 1, PF1 = 0, PF0 = 1 while PLL option is enabled

This is detailed in Table 125.

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