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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPSD3422 데이터시트(PDF) 269 Page - STMicroelectronics |
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UPSD3422 데이터시트(HTML) 269 Page - STMicroelectronics |
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269 / 293 page  uPSD34xx DC and AC parameters 269/293 Figure 99. External READ cycle (80-pin device only) Table 159. External READ cycle AC characteristics (3V or 5V device) Note: 1 BUSCON Register is configured for 4 PFQCLK. 2 Refer to Table 160 for “n” and “m” values. Table 160. n, m, and x, y values Symbol Parameter 40MHz Oscillator(1) Variable Oscillator 1/tCLCL = 3 to 40MHz Unit Min Max Min Max tLHLL ALE pulse width 17 tCLCL – 8 ns tAVLL Address setup to ALE 13 tCLCL – 12 ns tLLAX Address hold after ALE 7.5 0.5tCLCL – 5 ns tLLRL ALE to RD 7.5 0.5tCLCL – 5 ns tRLRH RD pulse width(2) 40 ntCLCL – 10 ns tRXIX Input data hold after RD 22 ns tRHIZ Input data float after RD 10.5 0.5tCLCL – 2 ns tAVDX Address to valid data in(2) 70 mtCLCL – 5 ns tAZRL Address float to RD –2 –2 ns tAVQV Address valid to latched address out on Ports A and B 35.5 (3V) 1.5tCLCL – 2 ns 28 (5V) tCLCL – 9.5 ns tAVLL tRLRH tRXDZ MCU AD0 - AD7 LATCHED MCU A8 - A15 AI10471 tLHLL ALE RD tLLRL A0-A7 tLLAX tAZRL tAVDV A0-A7 tRXDX tAVQV A8-A15 DATA IN A8-A15 # of PFQCLK in BUSCON Reg. READ Cycle WRITE Cycle nm x y 42 3 2 1 53 4 3 2 |
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