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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPSD3422 데이터시트(PDF) 270 Page - STMicroelectronics |
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UPSD3422 데이터시트(HTML) 270 Page - STMicroelectronics |
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270 / 293 page  DC and AC parameters uPSD34xx 270/293 Figure 100. External WRITE cycle (80-pin device only) Table 161. External WRITE cycle AC characteristics (3V or 5V device) 64 5 4 3 75 6 5 4 Symbol Parameter 40MHz Oscillator(1) Variable Oscillator 1/tCLCL = 3 to 40MHz Unit Min Max Min Max tLHLL ALE pulse width 17 tCLCL – 8 ns tAVLL Address Setup to ALE 13 tCLCL – 12 ns tLLAX Address hold after ALE 7.5 0.5tCLCL – 5 ns tWLWH WR pulse width(2) 40 xtCLCL – 10 ns tLLWL ALE to WR 7.5 0.5tCLCL – 5 ns tAVWL Address (A0-A7) valid to WR(3) 32.5 1.5tCLCL – 5 ns tWHLH WR High to ALE High 9.5 9.5 0.5tCLCL – 3 0.5tCLCL + 2 ns tQVWH Data setup before WR(y) 20 ytCLCL – 5 ns tWHQX Data hold after WR 9.5 14.5 0.5tCLCL – 3 0.5tCLCL + 2 ns tAVQV Address valid to Latched Address out on Ports A and B 35.5 (3V) 1.5tCLCL – 2 ns 28 (5V) tCLCL – 9.5 ns # of PFQCLK in BUSCON Reg. READ Cycle WRITE Cycle nm x y LATCHED MCU A8 - A15 MCU AD0 - AD7 ALE WR RD A8-A15 A8-A15 tLLWL tWLWH tAVLL tLHLL tQVWH DATA OUT A0-A7 DATA IN A0-A7 tLLAX tAVWL tAVQV tWHQX tWHLH AI10472 |
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