UPSD3422 datasheet(273/293 Pages) STMICROELECTRONICS

273 / 293 page

uPSD34xx

DC and AC parameters

273/293

Note:

Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by

given amount

2tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR,

PSEN and ALE to CPLD combinatorial output (80-pin package only)

Table 166.

CPLD combinatorial timing (3V PSD module)

Note:

Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by

given amount

2tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR,

PSEN and ALE to CPLD combinatorial output (80-pin package only)

Figure 102. Synchronous Clock Mode Timing – PLD

tARPW

CPLD Register Clear or

Preset Pulse Width

+ 10

tARD

CPLD Array Delay

Any

macrocell

+ 2

Symbol

Parameter

Conditions

Min

Max

Aloc

Turbo

Off

Slew

rate(1)

Unit

Symbol

Parameter

Conditions

Min

Max

Aloc

Turbo

Off

Slew

rate(1)

Unit

tPD

(2)

CPLD Input Pin/Feedback

to CPLD Combinatorial

Output

+ 4

+ 15

– 6

tEA

CPLD Input to CPLD

Output Enable

+ 15

– 6

tER

CPLD Input to CPLD

Output Disable

+ 15

– 6

tARP

CPLD Register Clear or

Preset Delay

+ 15

– 6

tARPW

CPLD Register Clear or

Preset Pulse Width

+ 15

tARD

CPLD Array Delay

Any

macrocell

+ 4

tCH

tCL

tCO

CLKIN

INPUT

REGISTERED

OUTPUT

AI02860

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