TMP86CS49FG datasheet(201/252 Pages) TOSHIBA

201 / 252 page

Page 187

TMP86CS49FG

If received data is not read out from SIO2RDB receive error occurs immediately after shift opera-

tion is finished. Then INTSIO2 interrupt request is generated after SIO2SR<RXERR> is set to “1”.

(3) Stopping the receive operation

There are two ways for stopping the receive operation.

• The way of clearing SIO2CR<SIOS>.

When SIO2CR<SIOS> is cleared to “0”, receive operation is stopped after all of the data is

finished to receive. When receive operation is finished, SIO2SR<SIOF> is cleared to “0”.

In external clock operation, SIO2CR<SIOS> must be cleared to “0” before SIO2SR<SEF> is

set to “1” by starting the next shift operation.

• The way of setting SIO2CR<SIOINH>.

Receive operation is stopped immediately after SIO2CR<SIOINH> is set to “1”. In this case,

SIO2CR<SIOS>, SIO2SR register, SIO2RDB register and SIO2TDB register are initialized.

Figure 15-10 Example of Internal Clock and MSB Receive Mode

A6 A5 A4 A3 A2 A1

B7 B6 B5 B4 B3 B2 B1

C6 C5 C4 C3 C2 C1 C0

Automatic wait

Start shift

operation

Start shift

operation

Start shift

operation

Writing transmit

data A

Writing transmit

data B

Clearing SIOS

Writing transmit

data C

SIO2CR<SIOS>

SIO2SR<SIOF>

SIO2SR<SEF>

SCK2

SI2 pin

SIO2SR<RXF>

INTSIO2

interrupt

request

SIO2RDB

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