TMP86CS49FG datasheet(204/252 Pages) TOSHIBA

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15. Synchronous Serial Interface (SIO2)

15.3 Function

TMP86CS49FG

(2) During the transmit/receive operation

When data is written to SIO2TDB, SIO2SR<TXF> is cleared to “0” and when a data is read from

SIO2RDB, SIO2SR<RXF> is cleared to “0”.

In internal clock operation, in case of the condition described below, the serial clock stops to “H”

level by an automatic-wait function when all of the bit set in the data has been transmitted.

• Next transmit data is not written to SIO2TDB after reading a received data from SIO2RDB.

• Received data is not read from SIO2RDB after writing a next transmit data to SIO2TDB.

• Neither SIO2TDB nor SIO2RDB is accessed after transmission.

The automatic wait function is released by writing the next transmit data to SIO2TDB after reading

the received data from SIO2RDB, or reading the received data from SIO2RDB after writing the next

data to SIO2TDB.

Then, transmit/receive operation is restarted after maximum 1 cycle of serial clock.

In external clock operation, reading the received data from SIO2RDB and writing the next data to

SIO2TDB must be finished before the shift operation of the next data begins.

If the transmit data is not written to SIO2TDB after SIO2SR<TXF> is set to “1”, transmit error

occurs immediately after shift operation is started. When the transmit error occurred,

SIO2SR<TXERR> is set to “1”.

If received data is not read out from SIO2RDB before next shift operation starts after setting

SIO2SR<RXF> to “1”, receive error occurs immediately after shift operation is finished. When the

receive error has occurred, SIO2SR<RXERR> is set to “1”.

(3) Stopping the transmit/receive operation

There are two ways for stopping the transmit/receive operation.

• The way of clearing SIO2CR<SIOS>.

When SIO2CR<SIOS> is cleared to “0”, transmit/receive operation is stopped after all trans-

fer of the data is finished. When transmit/receive operation is finished, SIO2SR<SIOF> is

cleared to “0” and SO2 pin is kept in high level.

In external clock operation, SIO2CR<SIOS> must be cleared to “0” before SIO2SR<SEF> is

set to “1” by beginning next transfer.

• The way of setting SIO2CR<SIOINH>.

Transmit/receive operation is stopped immediately after SIO2CR<SIOINH> is set to “1”. In

this case, SIO2CR<SIOS>, SIO2SR register, SIO2RDB register and SIO2TDB register are

initialized.

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