TBD datasheet(3/80 Pages) FREESCALE

3 / 80 page

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

Figure 1. MSC8144E Block Diagram

Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram

JTAG

RMU

SRIO

Note: The arrow direction indicates master or slave.

128-bit at

DDR Interface 16/32-bit at 400 MHz data rate

I/O-Interrupt

Concentrator

UART

Clocks

Timers

Reset

Semaphores

Other

DDR

10 Mbytes

Memory

512 Kbytes

Memory

CLASS

128 Kbyte

ICache

PCI 32-bit

Ser. RapidIO

Subsystem

Modules

QUICC Engine™

Ether-

Dual RISC

ATM

16-bit/8-bit

10/100/1000 Mbps

Subsystem

400 MHz

Processors

Eight TDMs

33/66 MHz

1x/4x

256-Channels each

Four DSP

Subsystems

Ether-

Boot ROM

I2C

Virtual

Interrupts

Controller

UTOPIA

SPI

net

Instruction

Cache

Address

Translation

Task

Protection

Data

Cache

(WTB)

(WBB)

EPIC

Interrupts

P-bus

Xa-bus

Xb-bus

DQBus

Debug Support

OCE30

Bus Interface

MMU

Timer

Two Internal Buses

(128 bits wide each)

IQBus

DPU

SC3400

Core

TWB

Write-

Through

Buffer

Write-

Back

Buffer

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