TBD datasheet(40/80 Pages) FREESCALE

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MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Electrical Characteristics

Freescale Semiconductor

Figure 9 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).

MDQ/MECC/MDM output setup with respect to MDQS5

•400 MHz

•333 MHz

•266 MHz

•200 MHz

tDDKHDS,

tDDKLDS

700

900

1100

1200

—

MDQ/MECC/MDM output hold with respect to MDQS5

•400 MHz

•333 MHz

•266 MHz

•200 MHz

tDDKHDX,

tDDKLDX

700

900

1100

1200

—

MDQS preamble start6

tDDKHMP

–0.5

× tMCK – 0.6

–0.5

× tMCK +0.6

MDQS epilogue end6

tDDKHME

–0.6

0.6

Notes:

The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

All MCK/MCK referenced measurements are made from the crossing of the two signals

±0.1 V.

ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the

ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by

1/2 applied cycle.

Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)

from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control

of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the

CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same

adjustment value. See the MSC8144 Reference Manual for a description and understanding of the timing modifications

enabled by use of these bits.

Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that tDDKHMP follows the

symbol conventions described in note 1.

At recommended operating conditions with VDDDDR (1.8 V or 2.5 V) ± 5%.

Figure 9. Timing for tDDKHMH

Table 28. DDR SDRAM Output AC Timing Specifications (continued)

Parameter

Symbol 1

Min

Max

Unit

MDQS

MCK[n]

tMCK

tDDKHMHmax) = 0.6 ns

tDDKHMH(min) = –0.6 ns

MDQS

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