TBD datasheet(55/80 Pages) FREESCALE

55 / 80 page

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

Figure 27 provides the AC test load.

Figure 28 shows the MII receive AC timing diagram.

2.7.10.4

RMII Transmit and Receive AC Timing Specifications

Table 48 provides the RMII transmit and receive AC timing specifications.

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

tMRDVKH

10.0

—

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

tMRDXKH

2—

RX_CLK clock rise

tMRXR

1.0

4.0

RX_CLK clock fall time

tMRXF

1.0

4.0

Notes:

Typical RX_CLK period (tMRX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.

Program GCR4 as 0x00030CC3.

Figure 27. AC Test Load

Figure 28. MII Receive AC Timing

Table 48. RMII Transmit and Receive AC Timing Specifications

Parameter/Condition

Symbol 1

Min

Max

Unit

REF_CLK duty cycle

tRMXH/tRMX

REF_CLK to RMII data TXD[1–0], TX_EN delay

tRMTKHDX

210

RXD[1–0], CRS_DV, RX_ER setup time to REF_CLK

tRMRDVKH

4.0

—

RXD[1–0], CRS_DV, RX_ER hold time to REF_CLK

tRMRDXKH

2.0

—

REF_CLK data clock rise

tRMXR

1.0

4.0

REF_CLK data clock fall

tRMXF

1.0

4.0

Typical REF_CLK clock period (tRMX) is 20 ns

Notes:

Typical REF_CLK clock period (tRMX) is 20 ns

Program GCR4 as 0x00001405

Table 47. MII Receive AC Timing Specifications (continued)

Parameter/Condition

Symbol 1

Min

Max

Unit

Output

Z0 = 50 Ω

VDDGE/2

RL = 50 Ω

RX_CLK

RXD[3:0]

tMRDXKH

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER

tMRDVKH

Valid Data

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