TBD datasheet(64/80 Pages) FREESCALE

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MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Hardware Design Considerations

Freescale Semiconductor

Hardware Design Considerations

The following sections discuss areas to consider when the MSC8144E device is designed into a system.

3.1

Start-up Sequencing Recommendations

3.1.1

Power-on Sequence

Use the following guidelines for power-on sequencing:

•

There are no dependencies in power-on/power-off sequence between VDDM3 and VDD supplies.

•

There are no dependencies in power-on/power-off sequence between RapidIO supplies: VDDSXC, VDDSXP,

VDDRIOPLL and other MSC8144E supplies.

•VDDPLL should be coupled with the VDD power rail with extremely low impedance path.

External voltage applied to any input line must not exceed the related to this port I/O supply by more than 0.6 V at any time,

including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for

configuration purposes. This is an acceptable exception to the rule during start-up. However, each such input can draw up to 80

mA per input pin per MSC8144E device in the system during start-up. An assertion of the inputs to the high voltage level before

power-up should be with slew rate less than 4V/ns.

The following supplies should rise before any other supplies in any sequence

•VDD and VDDPLL coupled together

•VDDM3

After the above supplies rise to 90% of their nominal value the following I/O supplies may rise in any sequence (see Figure 43):

•VDDGE1

•VDDGE2

•VDDIO

•

VDDDDR and MVREF coupled one to another. MVREF should be either at same time or after VDDDDR.

•VDDM3IO

•V25M3

Note:

This recommended power sequencing is different from the MSC8122/MSC8126.

If no pins that require VDDGE1 as a reference supply are used (see Table 1), VDDGE1 can be tied to GND.

If no pins that require VDDGE2 as a reference supply are used (see Table 1), VDDGE2 can be tied to GND.

If the DDR interface is not used, VDDDDR and MVREF can be tied to GND.

If the M3 memory is not used, VDDM3, VDDM3IO, and V25M3 can be tied to GND.

If the RapidIO interface is not used, VDDSX, VDDSXP, and VDDRIOPLL can be tied to GND.

Figure 43. VDDM3, VDDM3IO and V25M3 Power-on Sequence

VDDM3, VDD, and VDDPLL

90%

I/O supplies

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