AFE4490 datasheet(25/85 Pages) TI2

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ADCRST0

ADCRST1

ADCRST2

ADCRST3

ADC_RDY

Pulse Repetition Period

Data in ADC Registers

CONV1

CONV2

CONV3

CONV4

ADC registers hold contents of CONV1, CONV2, CONV3, and CONV4.

CONV1'

CONV2'

CONV3'

CONV4'

«&2191', CONV2', CONV3', CONV4'

(Generated by Device)

AFE4404

www.ti.com

SBAS689D – JUNE 2015 – REVISED DECEMBER 2016

Product Folder Links: AFE4404

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If a larger pulse duration is needed for the ADC_RDY interrupt, use PROG_TG_EN to enable a programmable timing signal to come out

of the ADC_RDY pin. The location of the signal can be set using the PROG_TG_STC and PROG_TG_ENDC counts.

The fourth ADCRST signal (ADCRST3) in a period also defines the start of the ADC_RDY pulse. The rising edge

of the ADC_RDY signal can be used as an interrupt by the MCU to readout the registers corresponding to the

preceding four conversions in that period. If any of the four conversion phases are not needed, then their

duration can be set to 0. However, the corresponding ADCRSTx pulse must still be defined. All four ADCRSTx

pulses must be defined in order to generate the ADC_RDY pulse. A scheme of the ADC_RDY pulse generation

is shown in Figure 34. The ADC_RDY pulse timing is shown in Table 8.

Figure 34. ADC_RDY Generation Scheme

Table 8. ADC_RDY Timing Details

TYP

MAX

UNIT

End of fourth ADC reset phase to start of

ADC_RDY pulse

(NUMAV + 1) × 200 × tADC

(NUMAV + 2) × 200 × tADC + 15

µs

ADC_RDY pulse duration

tADC

(1)

µs

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