전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

AFE4490 데이터시트(PDF) 55 Page - Texas Instruments

부품명 AFE4490
상세설명  AFE4404 Ultra-Small, Integrated AFE for Wearable, Optical, Heart-Rate Monitoring and Bio-Sensing
PDF  85 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments

AFE4490 데이터시트(HTML) 55 Page - Texas Instruments

Back Button AFE4490 Datasheet HTML 51Page - Texas Instruments AFE4490 Datasheet HTML 52Page - Texas Instruments AFE4490 Datasheet HTML 53Page - Texas Instruments AFE4490 Datasheet HTML 54Page - Texas Instruments AFE4490 Datasheet HTML 55Page - Texas Instruments AFE4490 Datasheet HTML 56Page - Texas Instruments AFE4490 Datasheet HTML 57Page - Texas Instruments AFE4490 Datasheet HTML 58Page - Texas Instruments AFE4490 Datasheet HTML 59Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 55 / 85 page
background image
55
AFE4404
www.ti.com
SBAS689D – JUNE 2015 – REVISED DECEMBER 2016
Product Folder Links: AFE4404
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
8.5.36 Register 29h (address = 29h) [reset = 0h]
Figure 73. Register 29h
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
15
14
13
12
11
10
9
8
0
0
0
0
0
0
ENABLE_
CLKOUT
0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
W-0h
7
6
5
4
3
2
1
0
0
0
0
CLKDIV_CLKOUT
0
W-0h
W-0h
W-0h
R/W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 55. Register 29h Field Descriptions
Bit
Field
Type
Reset
Description
23-10
0
W
0h
Must write 0.
9
ENABLE_CLKOUT
R/W
0h
In internal clock mode, the internally-generated clock can be
output on the CLK pin.
0 = Disables the clock output
1 = Enables CLKOUT generation and buffering on the CLK pin.
The frequency of the clock output on the CLK pin (in internal
clock mode) can be set using a programmable divider controlled
by the CLKDIV_CLKOUT register bit.
8-5
0
W
0h
Must write 0.
4-1
CLKDIV_CLKOUT
R/W
0h
Set the frequency of the clock output on the CLK pin (in the
internal clock mode), as shown in Table 56.
Table 56. CLKDIV_CLKOUT Register Settings
CLKDIV_CLKOUT REGISTER SETTINGS
DIVISION RATIO
FREQUENCY OF OUTPUT CLOCK IN MHz
0
1
4
1
2
2
2
4
1
3
8
0.5
4
16
0.25
5
32
0.125
6
64
0.0625
7
128
0.03125
8..15
Do not use
Do not use



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com