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AFE4490 데이터시트(PDF) 63 Page - Texas Instruments |
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AFE4490 데이터시트(HTML) 63 Page - Texas Instruments |
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63 / 85 page ![]() 63 AFE4404 www.ti.com SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 Product Folder Links: AFE4404 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated 8.5.50 Register 39h (address = 39h) [reset = 0h] Figure 87. Register 39h 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h 7 6 5 4 3 2 1 0 0 0 0 0 0 CLKDIV_PRF W-0h W-0h W-0h W-0h W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 71. Register 39h Field Descriptions Bit Field Type Reset Description 23-3 0 W 0h Must write 0. 2-0 CLKDIV_PRF R/W 0h Clock division ratio for the clock to the timing engine. For details, see Table 72. (1) Limit to 10 Hz. Table 72. CLKDIV_PRF Register Settings CLKDIV_PRF REGISTER SETTINGS DIVISION RATIO FREQUENCY OF THE TIMING CLOCK in MHz (When the ADC Clock is 4 MHz) LOWEST PRF SETTING (In Hz(1)) 0 1 4 61 1 Do not use Do not use Do not use 2 Do not use Do not use Do not use 3 Do not use Do not use Do not use 4 2 2 31 5 4 1 15 6 8 0.5 8 7 16 0.25 4 |
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