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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AFE4490 데이터시트(PDF) 8 Page - Texas Instruments |
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AFE4490 데이터시트(HTML) 8 Page - Texas Instruments |
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8 / 85 page  8 AFE4404 SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: AFE4404 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Electrical Characteristics (continued) Minimum and maximum specifications are at TA = –20°C to 70°C, typical specifications are at 25°C. TX_SUP = 4 V, RX_SUP = IO_SUP = 3 V, 100-Hz PRF, 8-MHz external clock (with CLKDIV_EXTMODE set to divide-by-2), detector CIN = 50 pF, and CLKDIV_PRF set to 1, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (6) In dynamic power-down mode for 90% and active mode for 10% of the period. (7) External clock mode with the external clock switched off. (8) LED currents set to 0 mA. (9) For full performance to be restored, a longer time as governed by tCHANNEL can be applicable. (10) tCHANNELscales inversely with the sampling duty cycle. CURRENT CONSUMPTION RX_SUP current Normal operation, in dynamic power-down mode(6) 300 µA Always ON receiver, external clock mode 620 Always ON receiver, internal oscillator mode 670 Hardware power-down (PWDN) mode(7) 3 Software power-down (PDNAFE) mode(7) 35 IO_SUP current Normal operation, in dynamic power-down mode(6) 20 µA Always ON receiver, external clock mode 20 Always ON receiver, internal oscillator mode 5 Hardware power-down (PWDN) mode(7) 3 Software power-down (PDNAFE) mode(7) 5 TX_SUP current Normal operation, in dynamic power-down mode(6)(8) 5 µA Always ON receiver, external clock mode(8) 25 Always ON receiver, internal oscillator mode(8) 25 Hardware power-down (PWDN) mode(7)(8) 2 Software power-down (PDNAFE) mode(7)(8) 2 TRANSIENT RECOVERY tACTIVE Recovery from PWDN mode Time for signal chain to be functional(9) 10 ms tCHANNEL Recovery from any event causing a change in signal characteristics PRF = 100 Hz, sampling duty cycle (each phase) of 2%(10) 200 ms DIGITAL INPUTS VIH High-level input voltage 0.9 × IO_SUP IO_SUP V VIL Low-level input voltage 0 0.1 × IO_SUP V DIGITAL OUTPUTS VOH High-level output voltage IO_SUP V VOL Low-level output voltage 0 V 7.6 Timing Requirements MIN TYP MAX UNIT tI2C_RISE I2C data rise time with a 10-kΩ pullup resistor with a 20-pF load from I 2C data to GND 1200 ns tI2C_FALL I2C data fall time (when the data line is pulled down by the AFE) with a 20-pF load from I2C data to GND 28 ns tADC_RDY_RISE ADC_RDY rise time (10% to 90%) with a 15-pF capacitive load to ground 21 ns tADC_RDY_FALL ADC_RDY fall time (90% to 10%) with a 15-pF capacitive load to ground 21 ns |
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